A poorly written OS for the x86 arch. (WIP)
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#include "pic.h"
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#include "io.h"
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void pic_send_eoi(uint8 irq) {
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if( irq >= 8 )
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outb(PIC2_CMD, PIC_EOI);
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outb(PIC1_CMD, PIC_EOI);
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}
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void pic_remap(uint offset_1, uint offset_2) {
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uint8 a1, a2;
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a1 = inb(PIC1_DATA);
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a2 = inb(PIC2_DATA);
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// Start the init sequance
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outb_w(PIC1_CMD, ICW_INIT_MASK);
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outb_w(PIC2_CMD, ICW_INIT_MASK);
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outb_w(PIC1_DATA, offset_1); // ICW2 master offset
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outb_w(PIC2_DATA, offset_2); // ICW2 slave offset
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outb_w(PIC1_DATA, 0x4);
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outb_w(PIC2_DATA, 0x2);
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outb_w(PIC1_DATA, ICW4_8086);
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outb_w(PIC2_DATA, ICW4_8086);
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// restore old masks
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outb(PIC1_DATA, a1);
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outb(PIC2_DATA, a2);
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}
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// disable the PIC
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// will probably never use this.
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void pic_disable() {
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outb(PIC1_DATA, 0xff);
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outb(PIC2_DATA, 0xff);
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}
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// set a specific irq
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void irq(uint8 idx, bool t) {
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uint16 port;
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uint8 data;
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if(idx < 8) {
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port = PIC1_DATA;
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} else {
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port = PIC2_DATA;
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idx -= 8;
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}
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if( t == true ) { // set irq
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data = inb(port) | (1 << idx);
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outb(port, data);
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} else { // clear irq
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data = inb(port) & ~(1 << idx);
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outb(port, data);
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}
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}
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static uint16 irq_reg(int ocw3) {
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outb(PIC1_CMD, ocw3);
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outb(PIC2_CMD, ocw3);
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return (inb(PIC2_CMD) << 8 | inb(PIC1_CMD));
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}
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uint16 get_irr() { return irq_reg(PIC_R_IRR); } // fetch IRR
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uint16 get_isr() { return irq_reg(PIC_R_ISR); } // fetch ISR
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